FIG. 1 (Prior Art) is a simplified diagram of a cellular telephone 1 having a Power Management Unit (PMU) 4 and a Central Processing Unit (CPU) 5. As illustrated in FIG. 1, cellular telephone 1 includes a small hole 2 and an ON/OFF push button 3. PMU 4 includes two input terminals T1 and T2. T1 and T2 are coupled externally to a supply voltage VDD by resistors R1 and R2 respectively. Small hole 2 contains a switch A that couples terminal T1 of PMU 4 to a digital logic low voltage GND when switch A is closed. ON/OFF push button 3 controls a switch B that couples terminal T2 of PMU 4 to the digital logic low voltage GND when switch B is closed. During normal operation, PMU 4 outputs supply voltages to CPU 5. A user may either press switch A inside small hole 2 to reset the cellular telephone or push ON/OFF push button 3 to enable/disable the cellular telephone.
FIG. 2 (Prior Art) is a table 9 that illustrates how cellular telephone 1 of FIG. 1 is configured through the use of two input terminals T1 and T2 of PMU 4. If cellular telephone 1 somehow malfunctions, then the user presses switch A inside small hole 2. Switch A closes and causes terminal T1 to be coupled to GND (T1 is denoted “0” in table 9). In response, PMU 4 outputs a first digital logic signal to reset CPU 5. On the other hand, if cellular telephone 1 is functioning properly, switch A remains open and the user uses ON/OFF push button 3 to either enable or disable the cellular telephone. In the example of FIG. 2, if the user pushes ON/OFF push button 3, then switch B closes and causes terminal T2 to be coupled to GND (T2 is denoted “0” in table 9). In response, PMU 4 outputs a second digital logic signal either to enable CPU 5 (if CPU 5 is previously disabled) or to disable CPU 5 (if CPU 5 previously is enabled). During normal operation, both switches A and B are released and terminals T1 and T2 have a digital logic high-voltage (T1 and T2 are denoted “1” in table 9). In response, PMU 4 outputs a third digital logic signal and remains in an idle state. As illustrated in FIG. 2, switch A has a higher priority over switch B. As long as switch A is pushed close, PMU 4 outputs the first digital logic signal to reset CPU 5 regardless whether switch B is pushed or released. However, two input terminals T1 and T2 are required for PMU 4 to be able to detect whether switch A and/or switch B is either pushed or released. PMU 4 then outputs a corresponding digital logic signal to either reset CPU 5 or enable/disable CPU 5. Improvements to the above-described PMU 4 are desired.